1. Field of the Invention
This invention relates to the forming of local area interconnects in an integrated circuit structure by selective deposition of conductive material on a patterned seed layer formed over a semiconductor substrate.
2. Description of the Related Art
Local area interconnects are used to provide electrical connections or interconnects between active and or passive devices of an integrated circuit structure at a level or levels below the customary metallization levels. Usually such interconnects involve the use of patterned polysilicon which has been doped to increase its conductivity. A doped layer of polysilicon is blanket deposited over the integrated circuit structure (or blanket deposited undoped and then doped), and then patterned, typically by masking and etching, to provide the desired interconnect or wiring structure. This is illustrated in prior art FIGS. 1 and 2, wherein a semiconductor substrate 2 is shown having portions of MOS devices formed therein comprising, for example, a source region 4 of a first MOS device and a source 6 of a second MOS device. An insulation layer 10 is shown formed over substrate 2 with contact openings 14 and 16, respectively, formed in insulation layer 10 to underlying sources 4 and 6. A doped polysilicon layer 20 is blanket deposited over insulation layer 10 and in contact openings 14 and 16. As shown in FIG. 2, polysilicon layer 20 is then patterned, using an appropriate mask and etching, to form conductive interconnect 22 to electrically interconnect sources 4 and 6 of the two MOS devices.
While such polysilicon interconnect structures are useful, extensive electrical interconnection at this level is usually avoided because of the less than satisfactory conductivity of the doped polysilicon, in comparison with upper metallization layers which are usually formed from a more conductive material, i.e., a metal such as aluminum.
Because of the desire to provide electrical interconnections at this level, and the low conductivity of doped polysilicon, attempts have been made to substitute more conductive materials such as metal silicides or metal nitrides for the polysilicon, due to the enhanced conductivity of, for example, titanium silicide in comparison to doped polysilicon. However, such technology has never become popular because of the relative difficulty in patterning such materials, in comparison with either polysilicon or upper metallization layers, when the material is first formed by a blanket deposition, similar to the blanket layer of polysilicon shown in FIG. 1, and then masked and etched to form the desired patterning of the layer of conductive material into interconnects, similar to the patterned polysilicon interconnect shown in FIG. 2.
However, if such problems could be overcome, the use of local area interconnect technology as part of the overall metallization interconnect technology for multiple level interconnects could provide improvements in device packing densities.